module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  reg  sync_0; // @[SynchronizerReg.scala 51:87]
  reg  sync_1; // @[SynchronizerReg.scala 51:87]
  reg  sync_2; // @[SynchronizerReg.scala 51:87]
  assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_0 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_1 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 54:22]
      sync_2 <= 1'h0;
    end else begin
      sync_2 <= io_d;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sync_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sync_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    sync_0 = 1'h0;
  end
  if (reset) begin
    sync_1 = 1'h0;
  end
  if (reset) begin
    sync_2 = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncResetSynchronizerShiftReg_w8_d3_i0(
  input        clock,
  input        reset,
  input  [7:0] io_d,
  output [7:0] io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_2_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_2_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_2_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_2_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_3_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_3_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_3_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_3_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_4_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_4_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_4_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_4_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_5_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_5_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_5_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_5_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_6_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_6_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_6_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_6_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_7_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_7_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_7_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_7_io_q; // @[ShiftReg.scala 45:23]
  wire  output_1 = output_chain_1_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_0 = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_3 = output_chain_3_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_2 = output_chain_2_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [3:0] io_q_lo = {output_3,output_2,output_1,output_0}; // @[Cat.scala 33:92]
  wire  output_5 = output_chain_5_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_4 = output_chain_4_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_7 = output_chain_7_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_6 = output_chain_6_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [3:0] io_q_hi = {output_7,output_6,output_5,output_4}; // @[Cat.scala 33:92]
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .reset(output_chain_reset),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_1 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_1_clock),
    .reset(output_chain_1_reset),
    .io_d(output_chain_1_io_d),
    .io_q(output_chain_1_io_q)
  );
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_2 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_2_clock),
    .reset(output_chain_2_reset),
    .io_d(output_chain_2_io_d),
    .io_q(output_chain_2_io_q)
  );
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_3 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_3_clock),
    .reset(output_chain_3_reset),
    .io_d(output_chain_3_io_d),
    .io_q(output_chain_3_io_q)
  );
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_4 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_4_clock),
    .reset(output_chain_4_reset),
    .io_d(output_chain_4_io_d),
    .io_q(output_chain_4_io_q)
  );
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_5 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_5_clock),
    .reset(output_chain_5_reset),
    .io_d(output_chain_5_io_d),
    .io_q(output_chain_5_io_q)
  );
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_6 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_6_clock),
    .reset(output_chain_6_reset),
    .io_d(output_chain_6_io_d),
    .io_q(output_chain_6_io_q)
  );
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_7 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_7_clock),
    .reset(output_chain_7_reset),
    .io_d(output_chain_7_io_d),
    .io_q(output_chain_7_io_q)
  );
  assign io_q = {io_q_hi,io_q_lo}; // @[Cat.scala 33:92]
  assign output_chain_clock = clock;
  assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_io_d = io_d[0]; // @[SynchronizerReg.scala 87:41]
  assign output_chain_1_clock = clock;
  assign output_chain_1_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_1_io_d = io_d[1]; // @[SynchronizerReg.scala 87:41]
  assign output_chain_2_clock = clock;
  assign output_chain_2_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_2_io_d = io_d[2]; // @[SynchronizerReg.scala 87:41]
  assign output_chain_3_clock = clock;
  assign output_chain_3_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_3_io_d = io_d[3]; // @[SynchronizerReg.scala 87:41]
  assign output_chain_4_clock = clock;
  assign output_chain_4_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_4_io_d = io_d[4]; // @[SynchronizerReg.scala 87:41]
  assign output_chain_5_clock = clock;
  assign output_chain_5_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_5_io_d = io_d[5]; // @[SynchronizerReg.scala 87:41]
  assign output_chain_6_clock = clock;
  assign output_chain_6_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_6_io_d = io_d[6]; // @[SynchronizerReg.scala 87:41]
  assign output_chain_7_clock = clock;
  assign output_chain_7_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_7_io_d = io_d[7]; // @[SynchronizerReg.scala 87:41]
endmodule
module AsyncResetSynchronizerShiftReg_w1_d3_i0(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .reset(output_chain_reset),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign output_chain_clock = clock;
  assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
endmodule
module AsyncValidSync(
  input   io_in,
  output  io_out,
  input   clock,
  input   reset
);
  wire  io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
  wire  io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
  wire  io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
  wire  io_out_source_valid_0_io_q; // @[ShiftReg.scala 45:23]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 io_out_source_valid_0 ( // @[ShiftReg.scala 45:23]
    .clock(io_out_source_valid_0_clock),
    .reset(io_out_source_valid_0_reset),
    .io_d(io_out_source_valid_0_io_d),
    .io_q(io_out_source_valid_0_io_q)
  );
  assign io_out = io_out_source_valid_0_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign io_out_source_valid_0_clock = clock;
  assign io_out_source_valid_0_reset = reset;
  assign io_out_source_valid_0_io_d = io_in; // @[ShiftReg.scala 47:16]
endmodule
module AsyncQueueSource(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits,
  output [31:0] io_async_mem_0,
  output [31:0] io_async_mem_1,
  output [31:0] io_async_mem_2,
  output [31:0] io_async_mem_3,
  output [31:0] io_async_mem_4,
  output [31:0] io_async_mem_5,
  output [31:0] io_async_mem_6,
  output [31:0] io_async_mem_7,
  output [31:0] io_async_mem_8,
  output [31:0] io_async_mem_9,
  output [31:0] io_async_mem_10,
  output [31:0] io_async_mem_11,
  output [31:0] io_async_mem_12,
  output [31:0] io_async_mem_13,
  output [31:0] io_async_mem_14,
  output [31:0] io_async_mem_15,
  output [31:0] io_async_mem_16,
  output [31:0] io_async_mem_17,
  output [31:0] io_async_mem_18,
  output [31:0] io_async_mem_19,
  output [31:0] io_async_mem_20,
  output [31:0] io_async_mem_21,
  output [31:0] io_async_mem_22,
  output [31:0] io_async_mem_23,
  output [31:0] io_async_mem_24,
  output [31:0] io_async_mem_25,
  output [31:0] io_async_mem_26,
  output [31:0] io_async_mem_27,
  output [31:0] io_async_mem_28,
  output [31:0] io_async_mem_29,
  output [31:0] io_async_mem_30,
  output [31:0] io_async_mem_31,
  output [31:0] io_async_mem_32,
  output [31:0] io_async_mem_33,
  output [31:0] io_async_mem_34,
  output [31:0] io_async_mem_35,
  output [31:0] io_async_mem_36,
  output [31:0] io_async_mem_37,
  output [31:0] io_async_mem_38,
  output [31:0] io_async_mem_39,
  output [31:0] io_async_mem_40,
  output [31:0] io_async_mem_41,
  output [31:0] io_async_mem_42,
  output [31:0] io_async_mem_43,
  output [31:0] io_async_mem_44,
  output [31:0] io_async_mem_45,
  output [31:0] io_async_mem_46,
  output [31:0] io_async_mem_47,
  output [31:0] io_async_mem_48,
  output [31:0] io_async_mem_49,
  output [31:0] io_async_mem_50,
  output [31:0] io_async_mem_51,
  output [31:0] io_async_mem_52,
  output [31:0] io_async_mem_53,
  output [31:0] io_async_mem_54,
  output [31:0] io_async_mem_55,
  output [31:0] io_async_mem_56,
  output [31:0] io_async_mem_57,
  output [31:0] io_async_mem_58,
  output [31:0] io_async_mem_59,
  output [31:0] io_async_mem_60,
  output [31:0] io_async_mem_61,
  output [31:0] io_async_mem_62,
  output [31:0] io_async_mem_63,
  output [31:0] io_async_mem_64,
  output [31:0] io_async_mem_65,
  output [31:0] io_async_mem_66,
  output [31:0] io_async_mem_67,
  output [31:0] io_async_mem_68,
  output [31:0] io_async_mem_69,
  output [31:0] io_async_mem_70,
  output [31:0] io_async_mem_71,
  output [31:0] io_async_mem_72,
  output [31:0] io_async_mem_73,
  output [31:0] io_async_mem_74,
  output [31:0] io_async_mem_75,
  output [31:0] io_async_mem_76,
  output [31:0] io_async_mem_77,
  output [31:0] io_async_mem_78,
  output [31:0] io_async_mem_79,
  output [31:0] io_async_mem_80,
  output [31:0] io_async_mem_81,
  output [31:0] io_async_mem_82,
  output [31:0] io_async_mem_83,
  output [31:0] io_async_mem_84,
  output [31:0] io_async_mem_85,
  output [31:0] io_async_mem_86,
  output [31:0] io_async_mem_87,
  output [31:0] io_async_mem_88,
  output [31:0] io_async_mem_89,
  output [31:0] io_async_mem_90,
  output [31:0] io_async_mem_91,
  output [31:0] io_async_mem_92,
  output [31:0] io_async_mem_93,
  output [31:0] io_async_mem_94,
  output [31:0] io_async_mem_95,
  output [31:0] io_async_mem_96,
  output [31:0] io_async_mem_97,
  output [31:0] io_async_mem_98,
  output [31:0] io_async_mem_99,
  output [31:0] io_async_mem_100,
  output [31:0] io_async_mem_101,
  output [31:0] io_async_mem_102,
  output [31:0] io_async_mem_103,
  output [31:0] io_async_mem_104,
  output [31:0] io_async_mem_105,
  output [31:0] io_async_mem_106,
  output [31:0] io_async_mem_107,
  output [31:0] io_async_mem_108,
  output [31:0] io_async_mem_109,
  output [31:0] io_async_mem_110,
  output [31:0] io_async_mem_111,
  output [31:0] io_async_mem_112,
  output [31:0] io_async_mem_113,
  output [31:0] io_async_mem_114,
  output [31:0] io_async_mem_115,
  output [31:0] io_async_mem_116,
  output [31:0] io_async_mem_117,
  output [31:0] io_async_mem_118,
  output [31:0] io_async_mem_119,
  output [31:0] io_async_mem_120,
  output [31:0] io_async_mem_121,
  output [31:0] io_async_mem_122,
  output [31:0] io_async_mem_123,
  output [31:0] io_async_mem_124,
  output [31:0] io_async_mem_125,
  output [31:0] io_async_mem_126,
  output [31:0] io_async_mem_127,
  input  [7:0]  io_async_ridx,
  output [7:0]  io_async_widx,
  input         io_async_safe_ridx_valid,
  output        io_async_safe_widx_valid,
  output        io_async_safe_source_reset_n,
  input         io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [31:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [31:0] _RAND_101;
  reg [31:0] _RAND_102;
  reg [31:0] _RAND_103;
  reg [31:0] _RAND_104;
  reg [31:0] _RAND_105;
  reg [31:0] _RAND_106;
  reg [31:0] _RAND_107;
  reg [31:0] _RAND_108;
  reg [31:0] _RAND_109;
  reg [31:0] _RAND_110;
  reg [31:0] _RAND_111;
  reg [31:0] _RAND_112;
  reg [31:0] _RAND_113;
  reg [31:0] _RAND_114;
  reg [31:0] _RAND_115;
  reg [31:0] _RAND_116;
  reg [31:0] _RAND_117;
  reg [31:0] _RAND_118;
  reg [31:0] _RAND_119;
  reg [31:0] _RAND_120;
  reg [31:0] _RAND_121;
  reg [31:0] _RAND_122;
  reg [31:0] _RAND_123;
  reg [31:0] _RAND_124;
  reg [31:0] _RAND_125;
  reg [31:0] _RAND_126;
  reg [31:0] _RAND_127;
  reg [31:0] _RAND_128;
  reg [31:0] _RAND_129;
  reg [31:0] _RAND_130;
`endif // RANDOMIZE_REG_INIT
  wire  ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
  wire [7:0] ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire [7:0] ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_clock; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_reset; // @[AsyncQueue.scala 100:32]
  wire  source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_clock; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_reset; // @[AsyncQueue.scala 101:32]
  wire  sink_extend_io_in; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_io_out; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_clock; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_reset; // @[AsyncQueue.scala 103:30]
  wire  sink_valid_io_in; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_io_out; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_clock; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_reset; // @[AsyncQueue.scala 104:30]
  reg [31:0] mem_0; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_1; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_2; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_3; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_4; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_5; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_6; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_7; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_8; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_9; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_10; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_11; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_12; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_13; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_14; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_15; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_16; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_17; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_18; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_19; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_20; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_21; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_22; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_23; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_24; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_25; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_26; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_27; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_28; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_29; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_30; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_31; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_32; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_33; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_34; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_35; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_36; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_37; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_38; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_39; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_40; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_41; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_42; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_43; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_44; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_45; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_46; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_47; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_48; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_49; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_50; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_51; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_52; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_53; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_54; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_55; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_56; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_57; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_58; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_59; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_60; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_61; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_62; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_63; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_64; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_65; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_66; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_67; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_68; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_69; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_70; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_71; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_72; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_73; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_74; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_75; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_76; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_77; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_78; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_79; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_80; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_81; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_82; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_83; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_84; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_85; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_86; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_87; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_88; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_89; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_90; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_91; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_92; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_93; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_94; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_95; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_96; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_97; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_98; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_99; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_100; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_101; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_102; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_103; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_104; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_105; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_106; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_107; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_108; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_109; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_110; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_111; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_112; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_113; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_114; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_115; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_116; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_117; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_118; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_119; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_120; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_121; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_122; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_123; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_124; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_125; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_126; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_127; // @[AsyncQueue.scala 80:16]
  wire  _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  sink_ready = sink_valid_io_out;
  wire  _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
  reg [7:0] widx_widx_bin; // @[AsyncQueue.scala 52:25]
  wire [7:0] _GEN_256 = {{7'd0}, _widx_T_1}; // @[AsyncQueue.scala 53:43]
  wire [7:0] _widx_incremented_T_1 = widx_widx_bin + _GEN_256; // @[AsyncQueue.scala 53:43]
  wire [7:0] widx_incremented = _widx_T_2 ? 8'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala 53:23]
  wire [7:0] _GEN_257 = {{1'd0}, widx_incremented[7:1]}; // @[AsyncQueue.scala 54:17]
  wire [7:0] widx = widx_incremented ^ _GEN_257; // @[AsyncQueue.scala 54:17]
  wire [7:0] ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [7:0] _ready_T = ridx ^ 8'hc0; // @[AsyncQueue.scala 83:44]
  wire [6:0] _index_T_2 = {io_async_widx[7], 6'h0}; // @[AsyncQueue.scala 85:93]
  wire [6:0] index = io_async_widx[6:0] ^ _index_T_2; // @[AsyncQueue.scala 85:64]
  reg  ready_reg; // @[AsyncQueue.scala 88:56]
  reg [7:0] widx_gray; // @[AsyncQueue.scala 91:55]
  AsyncResetSynchronizerShiftReg_w8_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
    .clock(ridx_ridx_gray_clock),
    .reset(ridx_ridx_gray_reset),
    .io_d(ridx_ridx_gray_io_d),
    .io_q(ridx_ridx_gray_io_q)
  );
  AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
    .io_in(source_valid_0_io_in),
    .io_out(source_valid_0_io_out),
    .clock(source_valid_0_clock),
    .reset(source_valid_0_reset)
  );
  AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
    .io_in(source_valid_1_io_in),
    .io_out(source_valid_1_io_out),
    .clock(source_valid_1_clock),
    .reset(source_valid_1_reset)
  );
  AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
    .io_in(sink_extend_io_in),
    .io_out(sink_extend_io_out),
    .clock(sink_extend_clock),
    .reset(sink_extend_reset)
  );
  AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
    .io_in(sink_valid_io_in),
    .io_out(sink_valid_io_out),
    .clock(sink_valid_clock),
    .reset(sink_valid_reset)
  );
  assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
  assign io_async_mem_0 = mem_0; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_1 = mem_1; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_2 = mem_2; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_3 = mem_3; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_4 = mem_4; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_5 = mem_5; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_6 = mem_6; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_7 = mem_7; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_8 = mem_8; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_9 = mem_9; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_10 = mem_10; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_11 = mem_11; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_12 = mem_12; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_13 = mem_13; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_14 = mem_14; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_15 = mem_15; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_16 = mem_16; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_17 = mem_17; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_18 = mem_18; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_19 = mem_19; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_20 = mem_20; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_21 = mem_21; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_22 = mem_22; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_23 = mem_23; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_24 = mem_24; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_25 = mem_25; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_26 = mem_26; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_27 = mem_27; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_28 = mem_28; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_29 = mem_29; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_30 = mem_30; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_31 = mem_31; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_32 = mem_32; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_33 = mem_33; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_34 = mem_34; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_35 = mem_35; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_36 = mem_36; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_37 = mem_37; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_38 = mem_38; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_39 = mem_39; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_40 = mem_40; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_41 = mem_41; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_42 = mem_42; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_43 = mem_43; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_44 = mem_44; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_45 = mem_45; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_46 = mem_46; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_47 = mem_47; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_48 = mem_48; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_49 = mem_49; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_50 = mem_50; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_51 = mem_51; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_52 = mem_52; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_53 = mem_53; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_54 = mem_54; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_55 = mem_55; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_56 = mem_56; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_57 = mem_57; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_58 = mem_58; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_59 = mem_59; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_60 = mem_60; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_61 = mem_61; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_62 = mem_62; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_63 = mem_63; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_64 = mem_64; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_65 = mem_65; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_66 = mem_66; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_67 = mem_67; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_68 = mem_68; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_69 = mem_69; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_70 = mem_70; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_71 = mem_71; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_72 = mem_72; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_73 = mem_73; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_74 = mem_74; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_75 = mem_75; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_76 = mem_76; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_77 = mem_77; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_78 = mem_78; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_79 = mem_79; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_80 = mem_80; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_81 = mem_81; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_82 = mem_82; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_83 = mem_83; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_84 = mem_84; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_85 = mem_85; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_86 = mem_86; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_87 = mem_87; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_88 = mem_88; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_89 = mem_89; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_90 = mem_90; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_91 = mem_91; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_92 = mem_92; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_93 = mem_93; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_94 = mem_94; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_95 = mem_95; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_96 = mem_96; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_97 = mem_97; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_98 = mem_98; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_99 = mem_99; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_100 = mem_100; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_101 = mem_101; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_102 = mem_102; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_103 = mem_103; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_104 = mem_104; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_105 = mem_105; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_106 = mem_106; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_107 = mem_107; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_108 = mem_108; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_109 = mem_109; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_110 = mem_110; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_111 = mem_111; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_112 = mem_112; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_113 = mem_113; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_114 = mem_114; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_115 = mem_115; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_116 = mem_116; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_117 = mem_117; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_118 = mem_118; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_119 = mem_119; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_120 = mem_120; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_121 = mem_121; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_122 = mem_122; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_123 = mem_123; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_124 = mem_124; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_125 = mem_125; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_126 = mem_126; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_127 = mem_127; // @[AsyncQueue.scala 96:31]
  assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
  assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
  assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
  assign ridx_ridx_gray_clock = clock;
  assign ridx_ridx_gray_reset = reset;
  assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
  assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
  assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
  assign source_valid_0_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 105:65]
  assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
  assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
  assign source_valid_1_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 106:65]
  assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
  assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
  assign sink_extend_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 107:65]
  assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
  assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
  assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
  always @(posedge clock) begin
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h0 == index) begin // @[AsyncQueue.scala 86:37]
        mem_0 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h1 == index) begin // @[AsyncQueue.scala 86:37]
        mem_1 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h2 == index) begin // @[AsyncQueue.scala 86:37]
        mem_2 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h3 == index) begin // @[AsyncQueue.scala 86:37]
        mem_3 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h4 == index) begin // @[AsyncQueue.scala 86:37]
        mem_4 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h5 == index) begin // @[AsyncQueue.scala 86:37]
        mem_5 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h6 == index) begin // @[AsyncQueue.scala 86:37]
        mem_6 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h7 == index) begin // @[AsyncQueue.scala 86:37]
        mem_7 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h8 == index) begin // @[AsyncQueue.scala 86:37]
        mem_8 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h9 == index) begin // @[AsyncQueue.scala 86:37]
        mem_9 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'ha == index) begin // @[AsyncQueue.scala 86:37]
        mem_10 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'hb == index) begin // @[AsyncQueue.scala 86:37]
        mem_11 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'hc == index) begin // @[AsyncQueue.scala 86:37]
        mem_12 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'hd == index) begin // @[AsyncQueue.scala 86:37]
        mem_13 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'he == index) begin // @[AsyncQueue.scala 86:37]
        mem_14 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'hf == index) begin // @[AsyncQueue.scala 86:37]
        mem_15 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h10 == index) begin // @[AsyncQueue.scala 86:37]
        mem_16 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h11 == index) begin // @[AsyncQueue.scala 86:37]
        mem_17 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h12 == index) begin // @[AsyncQueue.scala 86:37]
        mem_18 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h13 == index) begin // @[AsyncQueue.scala 86:37]
        mem_19 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h14 == index) begin // @[AsyncQueue.scala 86:37]
        mem_20 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h15 == index) begin // @[AsyncQueue.scala 86:37]
        mem_21 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h16 == index) begin // @[AsyncQueue.scala 86:37]
        mem_22 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h17 == index) begin // @[AsyncQueue.scala 86:37]
        mem_23 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h18 == index) begin // @[AsyncQueue.scala 86:37]
        mem_24 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h19 == index) begin // @[AsyncQueue.scala 86:37]
        mem_25 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h1a == index) begin // @[AsyncQueue.scala 86:37]
        mem_26 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h1b == index) begin // @[AsyncQueue.scala 86:37]
        mem_27 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h1c == index) begin // @[AsyncQueue.scala 86:37]
        mem_28 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h1d == index) begin // @[AsyncQueue.scala 86:37]
        mem_29 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h1e == index) begin // @[AsyncQueue.scala 86:37]
        mem_30 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h1f == index) begin // @[AsyncQueue.scala 86:37]
        mem_31 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h20 == index) begin // @[AsyncQueue.scala 86:37]
        mem_32 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h21 == index) begin // @[AsyncQueue.scala 86:37]
        mem_33 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h22 == index) begin // @[AsyncQueue.scala 86:37]
        mem_34 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h23 == index) begin // @[AsyncQueue.scala 86:37]
        mem_35 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h24 == index) begin // @[AsyncQueue.scala 86:37]
        mem_36 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h25 == index) begin // @[AsyncQueue.scala 86:37]
        mem_37 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h26 == index) begin // @[AsyncQueue.scala 86:37]
        mem_38 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h27 == index) begin // @[AsyncQueue.scala 86:37]
        mem_39 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h28 == index) begin // @[AsyncQueue.scala 86:37]
        mem_40 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h29 == index) begin // @[AsyncQueue.scala 86:37]
        mem_41 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h2a == index) begin // @[AsyncQueue.scala 86:37]
        mem_42 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h2b == index) begin // @[AsyncQueue.scala 86:37]
        mem_43 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h2c == index) begin // @[AsyncQueue.scala 86:37]
        mem_44 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h2d == index) begin // @[AsyncQueue.scala 86:37]
        mem_45 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h2e == index) begin // @[AsyncQueue.scala 86:37]
        mem_46 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h2f == index) begin // @[AsyncQueue.scala 86:37]
        mem_47 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h30 == index) begin // @[AsyncQueue.scala 86:37]
        mem_48 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h31 == index) begin // @[AsyncQueue.scala 86:37]
        mem_49 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h32 == index) begin // @[AsyncQueue.scala 86:37]
        mem_50 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h33 == index) begin // @[AsyncQueue.scala 86:37]
        mem_51 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h34 == index) begin // @[AsyncQueue.scala 86:37]
        mem_52 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h35 == index) begin // @[AsyncQueue.scala 86:37]
        mem_53 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h36 == index) begin // @[AsyncQueue.scala 86:37]
        mem_54 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h37 == index) begin // @[AsyncQueue.scala 86:37]
        mem_55 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h38 == index) begin // @[AsyncQueue.scala 86:37]
        mem_56 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h39 == index) begin // @[AsyncQueue.scala 86:37]
        mem_57 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h3a == index) begin // @[AsyncQueue.scala 86:37]
        mem_58 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h3b == index) begin // @[AsyncQueue.scala 86:37]
        mem_59 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h3c == index) begin // @[AsyncQueue.scala 86:37]
        mem_60 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h3d == index) begin // @[AsyncQueue.scala 86:37]
        mem_61 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h3e == index) begin // @[AsyncQueue.scala 86:37]
        mem_62 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h3f == index) begin // @[AsyncQueue.scala 86:37]
        mem_63 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h40 == index) begin // @[AsyncQueue.scala 86:37]
        mem_64 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h41 == index) begin // @[AsyncQueue.scala 86:37]
        mem_65 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h42 == index) begin // @[AsyncQueue.scala 86:37]
        mem_66 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h43 == index) begin // @[AsyncQueue.scala 86:37]
        mem_67 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h44 == index) begin // @[AsyncQueue.scala 86:37]
        mem_68 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h45 == index) begin // @[AsyncQueue.scala 86:37]
        mem_69 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h46 == index) begin // @[AsyncQueue.scala 86:37]
        mem_70 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h47 == index) begin // @[AsyncQueue.scala 86:37]
        mem_71 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h48 == index) begin // @[AsyncQueue.scala 86:37]
        mem_72 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h49 == index) begin // @[AsyncQueue.scala 86:37]
        mem_73 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h4a == index) begin // @[AsyncQueue.scala 86:37]
        mem_74 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h4b == index) begin // @[AsyncQueue.scala 86:37]
        mem_75 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h4c == index) begin // @[AsyncQueue.scala 86:37]
        mem_76 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h4d == index) begin // @[AsyncQueue.scala 86:37]
        mem_77 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h4e == index) begin // @[AsyncQueue.scala 86:37]
        mem_78 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h4f == index) begin // @[AsyncQueue.scala 86:37]
        mem_79 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h50 == index) begin // @[AsyncQueue.scala 86:37]
        mem_80 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h51 == index) begin // @[AsyncQueue.scala 86:37]
        mem_81 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h52 == index) begin // @[AsyncQueue.scala 86:37]
        mem_82 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h53 == index) begin // @[AsyncQueue.scala 86:37]
        mem_83 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h54 == index) begin // @[AsyncQueue.scala 86:37]
        mem_84 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h55 == index) begin // @[AsyncQueue.scala 86:37]
        mem_85 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h56 == index) begin // @[AsyncQueue.scala 86:37]
        mem_86 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h57 == index) begin // @[AsyncQueue.scala 86:37]
        mem_87 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h58 == index) begin // @[AsyncQueue.scala 86:37]
        mem_88 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h59 == index) begin // @[AsyncQueue.scala 86:37]
        mem_89 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h5a == index) begin // @[AsyncQueue.scala 86:37]
        mem_90 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h5b == index) begin // @[AsyncQueue.scala 86:37]
        mem_91 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h5c == index) begin // @[AsyncQueue.scala 86:37]
        mem_92 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h5d == index) begin // @[AsyncQueue.scala 86:37]
        mem_93 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h5e == index) begin // @[AsyncQueue.scala 86:37]
        mem_94 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h5f == index) begin // @[AsyncQueue.scala 86:37]
        mem_95 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h60 == index) begin // @[AsyncQueue.scala 86:37]
        mem_96 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h61 == index) begin // @[AsyncQueue.scala 86:37]
        mem_97 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h62 == index) begin // @[AsyncQueue.scala 86:37]
        mem_98 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h63 == index) begin // @[AsyncQueue.scala 86:37]
        mem_99 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h64 == index) begin // @[AsyncQueue.scala 86:37]
        mem_100 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h65 == index) begin // @[AsyncQueue.scala 86:37]
        mem_101 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h66 == index) begin // @[AsyncQueue.scala 86:37]
        mem_102 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h67 == index) begin // @[AsyncQueue.scala 86:37]
        mem_103 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h68 == index) begin // @[AsyncQueue.scala 86:37]
        mem_104 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h69 == index) begin // @[AsyncQueue.scala 86:37]
        mem_105 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h6a == index) begin // @[AsyncQueue.scala 86:37]
        mem_106 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h6b == index) begin // @[AsyncQueue.scala 86:37]
        mem_107 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h6c == index) begin // @[AsyncQueue.scala 86:37]
        mem_108 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h6d == index) begin // @[AsyncQueue.scala 86:37]
        mem_109 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h6e == index) begin // @[AsyncQueue.scala 86:37]
        mem_110 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h6f == index) begin // @[AsyncQueue.scala 86:37]
        mem_111 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h70 == index) begin // @[AsyncQueue.scala 86:37]
        mem_112 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h71 == index) begin // @[AsyncQueue.scala 86:37]
        mem_113 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h72 == index) begin // @[AsyncQueue.scala 86:37]
        mem_114 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h73 == index) begin // @[AsyncQueue.scala 86:37]
        mem_115 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h74 == index) begin // @[AsyncQueue.scala 86:37]
        mem_116 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h75 == index) begin // @[AsyncQueue.scala 86:37]
        mem_117 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h76 == index) begin // @[AsyncQueue.scala 86:37]
        mem_118 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h77 == index) begin // @[AsyncQueue.scala 86:37]
        mem_119 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h78 == index) begin // @[AsyncQueue.scala 86:37]
        mem_120 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h79 == index) begin // @[AsyncQueue.scala 86:37]
        mem_121 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h7a == index) begin // @[AsyncQueue.scala 86:37]
        mem_122 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h7b == index) begin // @[AsyncQueue.scala 86:37]
        mem_123 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h7c == index) begin // @[AsyncQueue.scala 86:37]
        mem_124 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h7d == index) begin // @[AsyncQueue.scala 86:37]
        mem_125 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h7e == index) begin // @[AsyncQueue.scala 86:37]
        mem_126 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      if (7'h7f == index) begin // @[AsyncQueue.scala 86:37]
        mem_127 <= io_enq_bits; // @[AsyncQueue.scala 86:37]
      end
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_widx_bin <= 8'h0;
    end else if (_widx_T_2) begin
      widx_widx_bin <= 8'h0;
    end else begin
      widx_widx_bin <= _widx_incremented_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 83:26]
      ready_reg <= 1'h0;
    end else begin
      ready_reg <= sink_ready & widx != _ready_T;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 54:17]
      widx_gray <= 8'h0;
    end else begin
      widx_gray <= widx_incremented ^ _GEN_257;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  mem_0 = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  mem_1 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  mem_2 = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  mem_3 = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  mem_4 = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  mem_5 = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  mem_6 = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  mem_7 = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  mem_8 = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  mem_9 = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  mem_10 = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  mem_11 = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  mem_12 = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  mem_13 = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  mem_14 = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  mem_15 = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  mem_16 = _RAND_16[31:0];
  _RAND_17 = {1{`RANDOM}};
  mem_17 = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  mem_18 = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  mem_19 = _RAND_19[31:0];
  _RAND_20 = {1{`RANDOM}};
  mem_20 = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  mem_21 = _RAND_21[31:0];
  _RAND_22 = {1{`RANDOM}};
  mem_22 = _RAND_22[31:0];
  _RAND_23 = {1{`RANDOM}};
  mem_23 = _RAND_23[31:0];
  _RAND_24 = {1{`RANDOM}};
  mem_24 = _RAND_24[31:0];
  _RAND_25 = {1{`RANDOM}};
  mem_25 = _RAND_25[31:0];
  _RAND_26 = {1{`RANDOM}};
  mem_26 = _RAND_26[31:0];
  _RAND_27 = {1{`RANDOM}};
  mem_27 = _RAND_27[31:0];
  _RAND_28 = {1{`RANDOM}};
  mem_28 = _RAND_28[31:0];
  _RAND_29 = {1{`RANDOM}};
  mem_29 = _RAND_29[31:0];
  _RAND_30 = {1{`RANDOM}};
  mem_30 = _RAND_30[31:0];
  _RAND_31 = {1{`RANDOM}};
  mem_31 = _RAND_31[31:0];
  _RAND_32 = {1{`RANDOM}};
  mem_32 = _RAND_32[31:0];
  _RAND_33 = {1{`RANDOM}};
  mem_33 = _RAND_33[31:0];
  _RAND_34 = {1{`RANDOM}};
  mem_34 = _RAND_34[31:0];
  _RAND_35 = {1{`RANDOM}};
  mem_35 = _RAND_35[31:0];
  _RAND_36 = {1{`RANDOM}};
  mem_36 = _RAND_36[31:0];
  _RAND_37 = {1{`RANDOM}};
  mem_37 = _RAND_37[31:0];
  _RAND_38 = {1{`RANDOM}};
  mem_38 = _RAND_38[31:0];
  _RAND_39 = {1{`RANDOM}};
  mem_39 = _RAND_39[31:0];
  _RAND_40 = {1{`RANDOM}};
  mem_40 = _RAND_40[31:0];
  _RAND_41 = {1{`RANDOM}};
  mem_41 = _RAND_41[31:0];
  _RAND_42 = {1{`RANDOM}};
  mem_42 = _RAND_42[31:0];
  _RAND_43 = {1{`RANDOM}};
  mem_43 = _RAND_43[31:0];
  _RAND_44 = {1{`RANDOM}};
  mem_44 = _RAND_44[31:0];
  _RAND_45 = {1{`RANDOM}};
  mem_45 = _RAND_45[31:0];
  _RAND_46 = {1{`RANDOM}};
  mem_46 = _RAND_46[31:0];
  _RAND_47 = {1{`RANDOM}};
  mem_47 = _RAND_47[31:0];
  _RAND_48 = {1{`RANDOM}};
  mem_48 = _RAND_48[31:0];
  _RAND_49 = {1{`RANDOM}};
  mem_49 = _RAND_49[31:0];
  _RAND_50 = {1{`RANDOM}};
  mem_50 = _RAND_50[31:0];
  _RAND_51 = {1{`RANDOM}};
  mem_51 = _RAND_51[31:0];
  _RAND_52 = {1{`RANDOM}};
  mem_52 = _RAND_52[31:0];
  _RAND_53 = {1{`RANDOM}};
  mem_53 = _RAND_53[31:0];
  _RAND_54 = {1{`RANDOM}};
  mem_54 = _RAND_54[31:0];
  _RAND_55 = {1{`RANDOM}};
  mem_55 = _RAND_55[31:0];
  _RAND_56 = {1{`RANDOM}};
  mem_56 = _RAND_56[31:0];
  _RAND_57 = {1{`RANDOM}};
  mem_57 = _RAND_57[31:0];
  _RAND_58 = {1{`RANDOM}};
  mem_58 = _RAND_58[31:0];
  _RAND_59 = {1{`RANDOM}};
  mem_59 = _RAND_59[31:0];
  _RAND_60 = {1{`RANDOM}};
  mem_60 = _RAND_60[31:0];
  _RAND_61 = {1{`RANDOM}};
  mem_61 = _RAND_61[31:0];
  _RAND_62 = {1{`RANDOM}};
  mem_62 = _RAND_62[31:0];
  _RAND_63 = {1{`RANDOM}};
  mem_63 = _RAND_63[31:0];
  _RAND_64 = {1{`RANDOM}};
  mem_64 = _RAND_64[31:0];
  _RAND_65 = {1{`RANDOM}};
  mem_65 = _RAND_65[31:0];
  _RAND_66 = {1{`RANDOM}};
  mem_66 = _RAND_66[31:0];
  _RAND_67 = {1{`RANDOM}};
  mem_67 = _RAND_67[31:0];
  _RAND_68 = {1{`RANDOM}};
  mem_68 = _RAND_68[31:0];
  _RAND_69 = {1{`RANDOM}};
  mem_69 = _RAND_69[31:0];
  _RAND_70 = {1{`RANDOM}};
  mem_70 = _RAND_70[31:0];
  _RAND_71 = {1{`RANDOM}};
  mem_71 = _RAND_71[31:0];
  _RAND_72 = {1{`RANDOM}};
  mem_72 = _RAND_72[31:0];
  _RAND_73 = {1{`RANDOM}};
  mem_73 = _RAND_73[31:0];
  _RAND_74 = {1{`RANDOM}};
  mem_74 = _RAND_74[31:0];
  _RAND_75 = {1{`RANDOM}};
  mem_75 = _RAND_75[31:0];
  _RAND_76 = {1{`RANDOM}};
  mem_76 = _RAND_76[31:0];
  _RAND_77 = {1{`RANDOM}};
  mem_77 = _RAND_77[31:0];
  _RAND_78 = {1{`RANDOM}};
  mem_78 = _RAND_78[31:0];
  _RAND_79 = {1{`RANDOM}};
  mem_79 = _RAND_79[31:0];
  _RAND_80 = {1{`RANDOM}};
  mem_80 = _RAND_80[31:0];
  _RAND_81 = {1{`RANDOM}};
  mem_81 = _RAND_81[31:0];
  _RAND_82 = {1{`RANDOM}};
  mem_82 = _RAND_82[31:0];
  _RAND_83 = {1{`RANDOM}};
  mem_83 = _RAND_83[31:0];
  _RAND_84 = {1{`RANDOM}};
  mem_84 = _RAND_84[31:0];
  _RAND_85 = {1{`RANDOM}};
  mem_85 = _RAND_85[31:0];
  _RAND_86 = {1{`RANDOM}};
  mem_86 = _RAND_86[31:0];
  _RAND_87 = {1{`RANDOM}};
  mem_87 = _RAND_87[31:0];
  _RAND_88 = {1{`RANDOM}};
  mem_88 = _RAND_88[31:0];
  _RAND_89 = {1{`RANDOM}};
  mem_89 = _RAND_89[31:0];
  _RAND_90 = {1{`RANDOM}};
  mem_90 = _RAND_90[31:0];
  _RAND_91 = {1{`RANDOM}};
  mem_91 = _RAND_91[31:0];
  _RAND_92 = {1{`RANDOM}};
  mem_92 = _RAND_92[31:0];
  _RAND_93 = {1{`RANDOM}};
  mem_93 = _RAND_93[31:0];
  _RAND_94 = {1{`RANDOM}};
  mem_94 = _RAND_94[31:0];
  _RAND_95 = {1{`RANDOM}};
  mem_95 = _RAND_95[31:0];
  _RAND_96 = {1{`RANDOM}};
  mem_96 = _RAND_96[31:0];
  _RAND_97 = {1{`RANDOM}};
  mem_97 = _RAND_97[31:0];
  _RAND_98 = {1{`RANDOM}};
  mem_98 = _RAND_98[31:0];
  _RAND_99 = {1{`RANDOM}};
  mem_99 = _RAND_99[31:0];
  _RAND_100 = {1{`RANDOM}};
  mem_100 = _RAND_100[31:0];
  _RAND_101 = {1{`RANDOM}};
  mem_101 = _RAND_101[31:0];
  _RAND_102 = {1{`RANDOM}};
  mem_102 = _RAND_102[31:0];
  _RAND_103 = {1{`RANDOM}};
  mem_103 = _RAND_103[31:0];
  _RAND_104 = {1{`RANDOM}};
  mem_104 = _RAND_104[31:0];
  _RAND_105 = {1{`RANDOM}};
  mem_105 = _RAND_105[31:0];
  _RAND_106 = {1{`RANDOM}};
  mem_106 = _RAND_106[31:0];
  _RAND_107 = {1{`RANDOM}};
  mem_107 = _RAND_107[31:0];
  _RAND_108 = {1{`RANDOM}};
  mem_108 = _RAND_108[31:0];
  _RAND_109 = {1{`RANDOM}};
  mem_109 = _RAND_109[31:0];
  _RAND_110 = {1{`RANDOM}};
  mem_110 = _RAND_110[31:0];
  _RAND_111 = {1{`RANDOM}};
  mem_111 = _RAND_111[31:0];
  _RAND_112 = {1{`RANDOM}};
  mem_112 = _RAND_112[31:0];
  _RAND_113 = {1{`RANDOM}};
  mem_113 = _RAND_113[31:0];
  _RAND_114 = {1{`RANDOM}};
  mem_114 = _RAND_114[31:0];
  _RAND_115 = {1{`RANDOM}};
  mem_115 = _RAND_115[31:0];
  _RAND_116 = {1{`RANDOM}};
  mem_116 = _RAND_116[31:0];
  _RAND_117 = {1{`RANDOM}};
  mem_117 = _RAND_117[31:0];
  _RAND_118 = {1{`RANDOM}};
  mem_118 = _RAND_118[31:0];
  _RAND_119 = {1{`RANDOM}};
  mem_119 = _RAND_119[31:0];
  _RAND_120 = {1{`RANDOM}};
  mem_120 = _RAND_120[31:0];
  _RAND_121 = {1{`RANDOM}};
  mem_121 = _RAND_121[31:0];
  _RAND_122 = {1{`RANDOM}};
  mem_122 = _RAND_122[31:0];
  _RAND_123 = {1{`RANDOM}};
  mem_123 = _RAND_123[31:0];
  _RAND_124 = {1{`RANDOM}};
  mem_124 = _RAND_124[31:0];
  _RAND_125 = {1{`RANDOM}};
  mem_125 = _RAND_125[31:0];
  _RAND_126 = {1{`RANDOM}};
  mem_126 = _RAND_126[31:0];
  _RAND_127 = {1{`RANDOM}};
  mem_127 = _RAND_127[31:0];
  _RAND_128 = {1{`RANDOM}};
  widx_widx_bin = _RAND_128[7:0];
  _RAND_129 = {1{`RANDOM}};
  ready_reg = _RAND_129[0:0];
  _RAND_130 = {1{`RANDOM}};
  widx_gray = _RAND_130[7:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    widx_widx_bin = 8'h0;
  end
  if (reset) begin
    ready_reg = 1'h0;
  end
  if (reset) begin
    widx_gray = 8'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockCrossingReg_w32(
  input         clock,
  input  [31:0] io_d,
  output [31:0] io_q,
  input         io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] cdc_reg; // @[Reg.scala 19:16]
  assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
  always @(posedge clock) begin
    if (io_en) begin // @[Reg.scala 20:18]
      cdc_reg <= io_d; // @[Reg.scala 20:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cdc_reg = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSink(
  input         clock,
  input         reset,
  input         io_deq_ready,
  output        io_deq_valid,
  output [31:0] io_deq_bits,
  input  [31:0] io_async_mem_0,
  input  [31:0] io_async_mem_1,
  input  [31:0] io_async_mem_2,
  input  [31:0] io_async_mem_3,
  input  [31:0] io_async_mem_4,
  input  [31:0] io_async_mem_5,
  input  [31:0] io_async_mem_6,
  input  [31:0] io_async_mem_7,
  input  [31:0] io_async_mem_8,
  input  [31:0] io_async_mem_9,
  input  [31:0] io_async_mem_10,
  input  [31:0] io_async_mem_11,
  input  [31:0] io_async_mem_12,
  input  [31:0] io_async_mem_13,
  input  [31:0] io_async_mem_14,
  input  [31:0] io_async_mem_15,
  input  [31:0] io_async_mem_16,
  input  [31:0] io_async_mem_17,
  input  [31:0] io_async_mem_18,
  input  [31:0] io_async_mem_19,
  input  [31:0] io_async_mem_20,
  input  [31:0] io_async_mem_21,
  input  [31:0] io_async_mem_22,
  input  [31:0] io_async_mem_23,
  input  [31:0] io_async_mem_24,
  input  [31:0] io_async_mem_25,
  input  [31:0] io_async_mem_26,
  input  [31:0] io_async_mem_27,
  input  [31:0] io_async_mem_28,
  input  [31:0] io_async_mem_29,
  input  [31:0] io_async_mem_30,
  input  [31:0] io_async_mem_31,
  input  [31:0] io_async_mem_32,
  input  [31:0] io_async_mem_33,
  input  [31:0] io_async_mem_34,
  input  [31:0] io_async_mem_35,
  input  [31:0] io_async_mem_36,
  input  [31:0] io_async_mem_37,
  input  [31:0] io_async_mem_38,
  input  [31:0] io_async_mem_39,
  input  [31:0] io_async_mem_40,
  input  [31:0] io_async_mem_41,
  input  [31:0] io_async_mem_42,
  input  [31:0] io_async_mem_43,
  input  [31:0] io_async_mem_44,
  input  [31:0] io_async_mem_45,
  input  [31:0] io_async_mem_46,
  input  [31:0] io_async_mem_47,
  input  [31:0] io_async_mem_48,
  input  [31:0] io_async_mem_49,
  input  [31:0] io_async_mem_50,
  input  [31:0] io_async_mem_51,
  input  [31:0] io_async_mem_52,
  input  [31:0] io_async_mem_53,
  input  [31:0] io_async_mem_54,
  input  [31:0] io_async_mem_55,
  input  [31:0] io_async_mem_56,
  input  [31:0] io_async_mem_57,
  input  [31:0] io_async_mem_58,
  input  [31:0] io_async_mem_59,
  input  [31:0] io_async_mem_60,
  input  [31:0] io_async_mem_61,
  input  [31:0] io_async_mem_62,
  input  [31:0] io_async_mem_63,
  input  [31:0] io_async_mem_64,
  input  [31:0] io_async_mem_65,
  input  [31:0] io_async_mem_66,
  input  [31:0] io_async_mem_67,
  input  [31:0] io_async_mem_68,
  input  [31:0] io_async_mem_69,
  input  [31:0] io_async_mem_70,
  input  [31:0] io_async_mem_71,
  input  [31:0] io_async_mem_72,
  input  [31:0] io_async_mem_73,
  input  [31:0] io_async_mem_74,
  input  [31:0] io_async_mem_75,
  input  [31:0] io_async_mem_76,
  input  [31:0] io_async_mem_77,
  input  [31:0] io_async_mem_78,
  input  [31:0] io_async_mem_79,
  input  [31:0] io_async_mem_80,
  input  [31:0] io_async_mem_81,
  input  [31:0] io_async_mem_82,
  input  [31:0] io_async_mem_83,
  input  [31:0] io_async_mem_84,
  input  [31:0] io_async_mem_85,
  input  [31:0] io_async_mem_86,
  input  [31:0] io_async_mem_87,
  input  [31:0] io_async_mem_88,
  input  [31:0] io_async_mem_89,
  input  [31:0] io_async_mem_90,
  input  [31:0] io_async_mem_91,
  input  [31:0] io_async_mem_92,
  input  [31:0] io_async_mem_93,
  input  [31:0] io_async_mem_94,
  input  [31:0] io_async_mem_95,
  input  [31:0] io_async_mem_96,
  input  [31:0] io_async_mem_97,
  input  [31:0] io_async_mem_98,
  input  [31:0] io_async_mem_99,
  input  [31:0] io_async_mem_100,
  input  [31:0] io_async_mem_101,
  input  [31:0] io_async_mem_102,
  input  [31:0] io_async_mem_103,
  input  [31:0] io_async_mem_104,
  input  [31:0] io_async_mem_105,
  input  [31:0] io_async_mem_106,
  input  [31:0] io_async_mem_107,
  input  [31:0] io_async_mem_108,
  input  [31:0] io_async_mem_109,
  input  [31:0] io_async_mem_110,
  input  [31:0] io_async_mem_111,
  input  [31:0] io_async_mem_112,
  input  [31:0] io_async_mem_113,
  input  [31:0] io_async_mem_114,
  input  [31:0] io_async_mem_115,
  input  [31:0] io_async_mem_116,
  input  [31:0] io_async_mem_117,
  input  [31:0] io_async_mem_118,
  input  [31:0] io_async_mem_119,
  input  [31:0] io_async_mem_120,
  input  [31:0] io_async_mem_121,
  input  [31:0] io_async_mem_122,
  input  [31:0] io_async_mem_123,
  input  [31:0] io_async_mem_124,
  input  [31:0] io_async_mem_125,
  input  [31:0] io_async_mem_126,
  input  [31:0] io_async_mem_127,
  output [7:0]  io_async_ridx,
  input  [7:0]  io_async_widx,
  output        io_async_safe_ridx_valid,
  input         io_async_safe_widx_valid,
  input         io_async_safe_source_reset_n,
  output        io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
  wire [7:0] widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire [7:0] widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
  wire [31:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
  wire [31:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
  wire  io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
  wire  sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
  wire  source_extend_io_in; // @[AsyncQueue.scala 171:31]
  wire  source_extend_io_out; // @[AsyncQueue.scala 171:31]
  wire  source_extend_clock; // @[AsyncQueue.scala 171:31]
  wire  source_extend_reset; // @[AsyncQueue.scala 171:31]
  wire  source_valid_io_in; // @[AsyncQueue.scala 172:31]
  wire  source_valid_io_out; // @[AsyncQueue.scala 172:31]
  wire  source_valid_clock; // @[AsyncQueue.scala 172:31]
  wire  source_valid_reset; // @[AsyncQueue.scala 172:31]
  wire  _ridx_T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  source_ready = source_valid_io_out;
  wire  _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
  reg [7:0] ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
  wire [7:0] _GEN_128 = {{7'd0}, _ridx_T_1}; // @[AsyncQueue.scala 53:43]
  wire [7:0] _ridx_incremented_T_1 = ridx_ridx_bin + _GEN_128; // @[AsyncQueue.scala 53:43]
  wire [7:0] ridx_incremented = _ridx_T_2 ? 8'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala 53:23]
  wire [7:0] _GEN_129 = {{1'd0}, ridx_incremented[7:1]}; // @[AsyncQueue.scala 54:17]
  wire [7:0] ridx = ridx_incremented ^ _GEN_129; // @[AsyncQueue.scala 54:17]
  wire [7:0] widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [6:0] _index_T_2 = {ridx[7], 6'h0}; // @[AsyncQueue.scala 152:75]
  wire [6:0] index = ridx[6:0] ^ _index_T_2; // @[AsyncQueue.scala 152:55]
  wire [31:0] _GEN_1 = 7'h1 == index ? io_async_mem_1 : io_async_mem_0; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_2 = 7'h2 == index ? io_async_mem_2 : _GEN_1; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_3 = 7'h3 == index ? io_async_mem_3 : _GEN_2; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_4 = 7'h4 == index ? io_async_mem_4 : _GEN_3; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_5 = 7'h5 == index ? io_async_mem_5 : _GEN_4; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_6 = 7'h6 == index ? io_async_mem_6 : _GEN_5; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_7 = 7'h7 == index ? io_async_mem_7 : _GEN_6; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_8 = 7'h8 == index ? io_async_mem_8 : _GEN_7; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_9 = 7'h9 == index ? io_async_mem_9 : _GEN_8; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_10 = 7'ha == index ? io_async_mem_10 : _GEN_9; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_11 = 7'hb == index ? io_async_mem_11 : _GEN_10; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_12 = 7'hc == index ? io_async_mem_12 : _GEN_11; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_13 = 7'hd == index ? io_async_mem_13 : _GEN_12; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_14 = 7'he == index ? io_async_mem_14 : _GEN_13; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_15 = 7'hf == index ? io_async_mem_15 : _GEN_14; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_16 = 7'h10 == index ? io_async_mem_16 : _GEN_15; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_17 = 7'h11 == index ? io_async_mem_17 : _GEN_16; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_18 = 7'h12 == index ? io_async_mem_18 : _GEN_17; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_19 = 7'h13 == index ? io_async_mem_19 : _GEN_18; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_20 = 7'h14 == index ? io_async_mem_20 : _GEN_19; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_21 = 7'h15 == index ? io_async_mem_21 : _GEN_20; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_22 = 7'h16 == index ? io_async_mem_22 : _GEN_21; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_23 = 7'h17 == index ? io_async_mem_23 : _GEN_22; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_24 = 7'h18 == index ? io_async_mem_24 : _GEN_23; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_25 = 7'h19 == index ? io_async_mem_25 : _GEN_24; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_26 = 7'h1a == index ? io_async_mem_26 : _GEN_25; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_27 = 7'h1b == index ? io_async_mem_27 : _GEN_26; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_28 = 7'h1c == index ? io_async_mem_28 : _GEN_27; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_29 = 7'h1d == index ? io_async_mem_29 : _GEN_28; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_30 = 7'h1e == index ? io_async_mem_30 : _GEN_29; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_31 = 7'h1f == index ? io_async_mem_31 : _GEN_30; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_32 = 7'h20 == index ? io_async_mem_32 : _GEN_31; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_33 = 7'h21 == index ? io_async_mem_33 : _GEN_32; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_34 = 7'h22 == index ? io_async_mem_34 : _GEN_33; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_35 = 7'h23 == index ? io_async_mem_35 : _GEN_34; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_36 = 7'h24 == index ? io_async_mem_36 : _GEN_35; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_37 = 7'h25 == index ? io_async_mem_37 : _GEN_36; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_38 = 7'h26 == index ? io_async_mem_38 : _GEN_37; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_39 = 7'h27 == index ? io_async_mem_39 : _GEN_38; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_40 = 7'h28 == index ? io_async_mem_40 : _GEN_39; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_41 = 7'h29 == index ? io_async_mem_41 : _GEN_40; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_42 = 7'h2a == index ? io_async_mem_42 : _GEN_41; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_43 = 7'h2b == index ? io_async_mem_43 : _GEN_42; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_44 = 7'h2c == index ? io_async_mem_44 : _GEN_43; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_45 = 7'h2d == index ? io_async_mem_45 : _GEN_44; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_46 = 7'h2e == index ? io_async_mem_46 : _GEN_45; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_47 = 7'h2f == index ? io_async_mem_47 : _GEN_46; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_48 = 7'h30 == index ? io_async_mem_48 : _GEN_47; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_49 = 7'h31 == index ? io_async_mem_49 : _GEN_48; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_50 = 7'h32 == index ? io_async_mem_50 : _GEN_49; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_51 = 7'h33 == index ? io_async_mem_51 : _GEN_50; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_52 = 7'h34 == index ? io_async_mem_52 : _GEN_51; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_53 = 7'h35 == index ? io_async_mem_53 : _GEN_52; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_54 = 7'h36 == index ? io_async_mem_54 : _GEN_53; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_55 = 7'h37 == index ? io_async_mem_55 : _GEN_54; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_56 = 7'h38 == index ? io_async_mem_56 : _GEN_55; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_57 = 7'h39 == index ? io_async_mem_57 : _GEN_56; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_58 = 7'h3a == index ? io_async_mem_58 : _GEN_57; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_59 = 7'h3b == index ? io_async_mem_59 : _GEN_58; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_60 = 7'h3c == index ? io_async_mem_60 : _GEN_59; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_61 = 7'h3d == index ? io_async_mem_61 : _GEN_60; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_62 = 7'h3e == index ? io_async_mem_62 : _GEN_61; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_63 = 7'h3f == index ? io_async_mem_63 : _GEN_62; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_64 = 7'h40 == index ? io_async_mem_64 : _GEN_63; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_65 = 7'h41 == index ? io_async_mem_65 : _GEN_64; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_66 = 7'h42 == index ? io_async_mem_66 : _GEN_65; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_67 = 7'h43 == index ? io_async_mem_67 : _GEN_66; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_68 = 7'h44 == index ? io_async_mem_68 : _GEN_67; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_69 = 7'h45 == index ? io_async_mem_69 : _GEN_68; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_70 = 7'h46 == index ? io_async_mem_70 : _GEN_69; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_71 = 7'h47 == index ? io_async_mem_71 : _GEN_70; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_72 = 7'h48 == index ? io_async_mem_72 : _GEN_71; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_73 = 7'h49 == index ? io_async_mem_73 : _GEN_72; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_74 = 7'h4a == index ? io_async_mem_74 : _GEN_73; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_75 = 7'h4b == index ? io_async_mem_75 : _GEN_74; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_76 = 7'h4c == index ? io_async_mem_76 : _GEN_75; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_77 = 7'h4d == index ? io_async_mem_77 : _GEN_76; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_78 = 7'h4e == index ? io_async_mem_78 : _GEN_77; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_79 = 7'h4f == index ? io_async_mem_79 : _GEN_78; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_80 = 7'h50 == index ? io_async_mem_80 : _GEN_79; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_81 = 7'h51 == index ? io_async_mem_81 : _GEN_80; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_82 = 7'h52 == index ? io_async_mem_82 : _GEN_81; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_83 = 7'h53 == index ? io_async_mem_83 : _GEN_82; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_84 = 7'h54 == index ? io_async_mem_84 : _GEN_83; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_85 = 7'h55 == index ? io_async_mem_85 : _GEN_84; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_86 = 7'h56 == index ? io_async_mem_86 : _GEN_85; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_87 = 7'h57 == index ? io_async_mem_87 : _GEN_86; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_88 = 7'h58 == index ? io_async_mem_88 : _GEN_87; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_89 = 7'h59 == index ? io_async_mem_89 : _GEN_88; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_90 = 7'h5a == index ? io_async_mem_90 : _GEN_89; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_91 = 7'h5b == index ? io_async_mem_91 : _GEN_90; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_92 = 7'h5c == index ? io_async_mem_92 : _GEN_91; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_93 = 7'h5d == index ? io_async_mem_93 : _GEN_92; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_94 = 7'h5e == index ? io_async_mem_94 : _GEN_93; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_95 = 7'h5f == index ? io_async_mem_95 : _GEN_94; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_96 = 7'h60 == index ? io_async_mem_96 : _GEN_95; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_97 = 7'h61 == index ? io_async_mem_97 : _GEN_96; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_98 = 7'h62 == index ? io_async_mem_98 : _GEN_97; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_99 = 7'h63 == index ? io_async_mem_99 : _GEN_98; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_100 = 7'h64 == index ? io_async_mem_100 : _GEN_99; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_101 = 7'h65 == index ? io_async_mem_101 : _GEN_100; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_102 = 7'h66 == index ? io_async_mem_102 : _GEN_101; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_103 = 7'h67 == index ? io_async_mem_103 : _GEN_102; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_104 = 7'h68 == index ? io_async_mem_104 : _GEN_103; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_105 = 7'h69 == index ? io_async_mem_105 : _GEN_104; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_106 = 7'h6a == index ? io_async_mem_106 : _GEN_105; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_107 = 7'h6b == index ? io_async_mem_107 : _GEN_106; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_108 = 7'h6c == index ? io_async_mem_108 : _GEN_107; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_109 = 7'h6d == index ? io_async_mem_109 : _GEN_108; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_110 = 7'h6e == index ? io_async_mem_110 : _GEN_109; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_111 = 7'h6f == index ? io_async_mem_111 : _GEN_110; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_112 = 7'h70 == index ? io_async_mem_112 : _GEN_111; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_113 = 7'h71 == index ? io_async_mem_113 : _GEN_112; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_114 = 7'h72 == index ? io_async_mem_114 : _GEN_113; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_115 = 7'h73 == index ? io_async_mem_115 : _GEN_114; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_116 = 7'h74 == index ? io_async_mem_116 : _GEN_115; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_117 = 7'h75 == index ? io_async_mem_117 : _GEN_116; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_118 = 7'h76 == index ? io_async_mem_118 : _GEN_117; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_119 = 7'h77 == index ? io_async_mem_119 : _GEN_118; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_120 = 7'h78 == index ? io_async_mem_120 : _GEN_119; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_121 = 7'h79 == index ? io_async_mem_121 : _GEN_120; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_122 = 7'h7a == index ? io_async_mem_122 : _GEN_121; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_123 = 7'h7b == index ? io_async_mem_123 : _GEN_122; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_124 = 7'h7c == index ? io_async_mem_124 : _GEN_123; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_125 = 7'h7d == index ? io_async_mem_125 : _GEN_124; // @[SynchronizerReg.scala 209:{18,18}]
  wire [31:0] _GEN_126 = 7'h7e == index ? io_async_mem_126 : _GEN_125; // @[SynchronizerReg.scala 209:{18,18}]
  reg  valid_reg; // @[AsyncQueue.scala 161:56]
  reg [7:0] ridx_gray; // @[AsyncQueue.scala 164:55]
  AsyncResetSynchronizerShiftReg_w8_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
    .clock(widx_widx_gray_clock),
    .reset(widx_widx_gray_reset),
    .io_d(widx_widx_gray_io_d),
    .io_q(widx_widx_gray_io_q)
  );
  ClockCrossingReg_w32 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
    .clock(io_deq_bits_deq_bits_reg_clock),
    .io_d(io_deq_bits_deq_bits_reg_io_d),
    .io_q(io_deq_bits_deq_bits_reg_io_q),
    .io_en(io_deq_bits_deq_bits_reg_io_en)
  );
  AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
    .io_in(sink_valid_0_io_in),
    .io_out(sink_valid_0_io_out),
    .clock(sink_valid_0_clock),
    .reset(sink_valid_0_reset)
  );
  AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
    .io_in(sink_valid_1_io_in),
    .io_out(sink_valid_1_io_out),
    .clock(sink_valid_1_clock),
    .reset(sink_valid_1_reset)
  );
  AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
    .io_in(source_extend_io_in),
    .io_out(source_extend_io_out),
    .clock(source_extend_clock),
    .reset(source_extend_reset)
  );
  AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
    .io_in(source_valid_io_in),
    .io_out(source_valid_io_out),
    .clock(source_valid_clock),
    .reset(source_valid_reset)
  );
  assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
  assign io_deq_bits = io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 211:{26,26}]
  assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
  assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
  assign io_async_safe_sink_reset_n = ~reset; // @[AsyncQueue.scala 189:25]
  assign widx_widx_gray_clock = clock;
  assign widx_widx_gray_reset = reset;
  assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
  assign io_deq_bits_deq_bits_reg_clock = clock;
  assign io_deq_bits_deq_bits_reg_io_d = 7'h7f == index ? io_async_mem_127 : _GEN_126; // @[SynchronizerReg.scala 209:{18,18}]
  assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx != widx; // @[AsyncQueue.scala 146:28]
  assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
  assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
  assign sink_valid_0_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
  assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
  assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
  assign sink_valid_1_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
  assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
  assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
  assign source_extend_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
  assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
  assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
  assign source_valid_reset = reset; // @[AsyncQueue.scala 176:34]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      ridx_ridx_bin <= 8'h0;
    end else if (_ridx_T_2) begin
      ridx_ridx_bin <= 8'h0;
    end else begin
      ridx_ridx_bin <= _ridx_incremented_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 146:28]
      valid_reg <= 1'h0;
    end else begin
      valid_reg <= source_ready & ridx != widx;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 54:17]
      ridx_gray <= 8'h0;
    end else begin
      ridx_gray <= ridx_incremented ^ _GEN_129;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ridx_ridx_bin = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  valid_reg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ridx_gray = _RAND_2[7:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    ridx_ridx_bin = 8'h0;
  end
  if (reset) begin
    valid_reg = 1'h0;
  end
  if (reset) begin
    ridx_gray = 8'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueue(
  input         clock,
  input         reset,
  input         io_enq_clock,
  input         io_enq_reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits,
  input         io_deq_clock,
  input         io_deq_reset,
  input         io_deq_ready,
  output        io_deq_valid,
  output [31:0] io_deq_bits
);
  wire  source_clock; // @[AsyncQueue.scala 224:22]
  wire  source_reset; // @[AsyncQueue.scala 224:22]
  wire  source_io_enq_ready; // @[AsyncQueue.scala 224:22]
  wire  source_io_enq_valid; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_enq_bits; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_0; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_1; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_2; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_3; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_4; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_5; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_6; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_7; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_8; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_9; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_10; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_11; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_12; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_13; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_14; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_15; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_16; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_17; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_18; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_19; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_20; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_21; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_22; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_23; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_24; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_25; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_26; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_27; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_28; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_29; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_30; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_31; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_32; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_33; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_34; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_35; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_36; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_37; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_38; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_39; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_40; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_41; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_42; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_43; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_44; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_45; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_46; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_47; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_48; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_49; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_50; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_51; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_52; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_53; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_54; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_55; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_56; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_57; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_58; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_59; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_60; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_61; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_62; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_63; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_64; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_65; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_66; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_67; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_68; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_69; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_70; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_71; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_72; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_73; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_74; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_75; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_76; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_77; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_78; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_79; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_80; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_81; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_82; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_83; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_84; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_85; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_86; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_87; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_88; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_89; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_90; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_91; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_92; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_93; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_94; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_95; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_96; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_97; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_98; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_99; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_100; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_101; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_102; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_103; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_104; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_105; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_106; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_107; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_108; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_109; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_110; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_111; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_112; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_113; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_114; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_115; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_116; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_117; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_118; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_119; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_120; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_121; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_122; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_123; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_124; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_125; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_126; // @[AsyncQueue.scala 224:22]
  wire [31:0] source_io_async_mem_127; // @[AsyncQueue.scala 224:22]
  wire [7:0] source_io_async_ridx; // @[AsyncQueue.scala 224:22]
  wire [7:0] source_io_async_widx; // @[AsyncQueue.scala 224:22]
  wire  source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 224:22]
  wire  source_io_async_safe_widx_valid; // @[AsyncQueue.scala 224:22]
  wire  source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 224:22]
  wire  source_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 224:22]
  wire  sink_clock; // @[AsyncQueue.scala 225:22]
  wire  sink_reset; // @[AsyncQueue.scala 225:22]
  wire  sink_io_deq_ready; // @[AsyncQueue.scala 225:22]
  wire  sink_io_deq_valid; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_deq_bits; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_0; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_1; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_2; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_3; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_4; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_5; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_6; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_7; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_8; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_9; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_10; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_11; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_12; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_13; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_14; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_15; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_16; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_17; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_18; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_19; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_20; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_21; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_22; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_23; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_24; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_25; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_26; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_27; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_28; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_29; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_30; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_31; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_32; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_33; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_34; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_35; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_36; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_37; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_38; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_39; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_40; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_41; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_42; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_43; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_44; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_45; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_46; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_47; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_48; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_49; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_50; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_51; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_52; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_53; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_54; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_55; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_56; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_57; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_58; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_59; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_60; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_61; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_62; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_63; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_64; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_65; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_66; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_67; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_68; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_69; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_70; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_71; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_72; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_73; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_74; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_75; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_76; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_77; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_78; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_79; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_80; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_81; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_82; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_83; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_84; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_85; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_86; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_87; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_88; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_89; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_90; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_91; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_92; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_93; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_94; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_95; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_96; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_97; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_98; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_99; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_100; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_101; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_102; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_103; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_104; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_105; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_106; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_107; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_108; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_109; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_110; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_111; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_112; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_113; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_114; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_115; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_116; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_117; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_118; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_119; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_120; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_121; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_122; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_123; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_124; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_125; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_126; // @[AsyncQueue.scala 225:22]
  wire [31:0] sink_io_async_mem_127; // @[AsyncQueue.scala 225:22]
  wire [7:0] sink_io_async_ridx; // @[AsyncQueue.scala 225:22]
  wire [7:0] sink_io_async_widx; // @[AsyncQueue.scala 225:22]
  wire  sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 225:22]
  wire  sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 225:22]
  wire  sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 225:22]
  wire  sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 225:22]
  AsyncQueueSource source ( // @[AsyncQueue.scala 224:22]
    .clock(source_clock),
    .reset(source_reset),
    .io_enq_ready(source_io_enq_ready),
    .io_enq_valid(source_io_enq_valid),
    .io_enq_bits(source_io_enq_bits),
    .io_async_mem_0(source_io_async_mem_0),
    .io_async_mem_1(source_io_async_mem_1),
    .io_async_mem_2(source_io_async_mem_2),
    .io_async_mem_3(source_io_async_mem_3),
    .io_async_mem_4(source_io_async_mem_4),
    .io_async_mem_5(source_io_async_mem_5),
    .io_async_mem_6(source_io_async_mem_6),
    .io_async_mem_7(source_io_async_mem_7),
    .io_async_mem_8(source_io_async_mem_8),
    .io_async_mem_9(source_io_async_mem_9),
    .io_async_mem_10(source_io_async_mem_10),
    .io_async_mem_11(source_io_async_mem_11),
    .io_async_mem_12(source_io_async_mem_12),
    .io_async_mem_13(source_io_async_mem_13),
    .io_async_mem_14(source_io_async_mem_14),
    .io_async_mem_15(source_io_async_mem_15),
    .io_async_mem_16(source_io_async_mem_16),
    .io_async_mem_17(source_io_async_mem_17),
    .io_async_mem_18(source_io_async_mem_18),
    .io_async_mem_19(source_io_async_mem_19),
    .io_async_mem_20(source_io_async_mem_20),
    .io_async_mem_21(source_io_async_mem_21),
    .io_async_mem_22(source_io_async_mem_22),
    .io_async_mem_23(source_io_async_mem_23),
    .io_async_mem_24(source_io_async_mem_24),
    .io_async_mem_25(source_io_async_mem_25),
    .io_async_mem_26(source_io_async_mem_26),
    .io_async_mem_27(source_io_async_mem_27),
    .io_async_mem_28(source_io_async_mem_28),
    .io_async_mem_29(source_io_async_mem_29),
    .io_async_mem_30(source_io_async_mem_30),
    .io_async_mem_31(source_io_async_mem_31),
    .io_async_mem_32(source_io_async_mem_32),
    .io_async_mem_33(source_io_async_mem_33),
    .io_async_mem_34(source_io_async_mem_34),
    .io_async_mem_35(source_io_async_mem_35),
    .io_async_mem_36(source_io_async_mem_36),
    .io_async_mem_37(source_io_async_mem_37),
    .io_async_mem_38(source_io_async_mem_38),
    .io_async_mem_39(source_io_async_mem_39),
    .io_async_mem_40(source_io_async_mem_40),
    .io_async_mem_41(source_io_async_mem_41),
    .io_async_mem_42(source_io_async_mem_42),
    .io_async_mem_43(source_io_async_mem_43),
    .io_async_mem_44(source_io_async_mem_44),
    .io_async_mem_45(source_io_async_mem_45),
    .io_async_mem_46(source_io_async_mem_46),
    .io_async_mem_47(source_io_async_mem_47),
    .io_async_mem_48(source_io_async_mem_48),
    .io_async_mem_49(source_io_async_mem_49),
    .io_async_mem_50(source_io_async_mem_50),
    .io_async_mem_51(source_io_async_mem_51),
    .io_async_mem_52(source_io_async_mem_52),
    .io_async_mem_53(source_io_async_mem_53),
    .io_async_mem_54(source_io_async_mem_54),
    .io_async_mem_55(source_io_async_mem_55),
    .io_async_mem_56(source_io_async_mem_56),
    .io_async_mem_57(source_io_async_mem_57),
    .io_async_mem_58(source_io_async_mem_58),
    .io_async_mem_59(source_io_async_mem_59),
    .io_async_mem_60(source_io_async_mem_60),
    .io_async_mem_61(source_io_async_mem_61),
    .io_async_mem_62(source_io_async_mem_62),
    .io_async_mem_63(source_io_async_mem_63),
    .io_async_mem_64(source_io_async_mem_64),
    .io_async_mem_65(source_io_async_mem_65),
    .io_async_mem_66(source_io_async_mem_66),
    .io_async_mem_67(source_io_async_mem_67),
    .io_async_mem_68(source_io_async_mem_68),
    .io_async_mem_69(source_io_async_mem_69),
    .io_async_mem_70(source_io_async_mem_70),
    .io_async_mem_71(source_io_async_mem_71),
    .io_async_mem_72(source_io_async_mem_72),
    .io_async_mem_73(source_io_async_mem_73),
    .io_async_mem_74(source_io_async_mem_74),
    .io_async_mem_75(source_io_async_mem_75),
    .io_async_mem_76(source_io_async_mem_76),
    .io_async_mem_77(source_io_async_mem_77),
    .io_async_mem_78(source_io_async_mem_78),
    .io_async_mem_79(source_io_async_mem_79),
    .io_async_mem_80(source_io_async_mem_80),
    .io_async_mem_81(source_io_async_mem_81),
    .io_async_mem_82(source_io_async_mem_82),
    .io_async_mem_83(source_io_async_mem_83),
    .io_async_mem_84(source_io_async_mem_84),
    .io_async_mem_85(source_io_async_mem_85),
    .io_async_mem_86(source_io_async_mem_86),
    .io_async_mem_87(source_io_async_mem_87),
    .io_async_mem_88(source_io_async_mem_88),
    .io_async_mem_89(source_io_async_mem_89),
    .io_async_mem_90(source_io_async_mem_90),
    .io_async_mem_91(source_io_async_mem_91),
    .io_async_mem_92(source_io_async_mem_92),
    .io_async_mem_93(source_io_async_mem_93),
    .io_async_mem_94(source_io_async_mem_94),
    .io_async_mem_95(source_io_async_mem_95),
    .io_async_mem_96(source_io_async_mem_96),
    .io_async_mem_97(source_io_async_mem_97),
    .io_async_mem_98(source_io_async_mem_98),
    .io_async_mem_99(source_io_async_mem_99),
    .io_async_mem_100(source_io_async_mem_100),
    .io_async_mem_101(source_io_async_mem_101),
    .io_async_mem_102(source_io_async_mem_102),
    .io_async_mem_103(source_io_async_mem_103),
    .io_async_mem_104(source_io_async_mem_104),
    .io_async_mem_105(source_io_async_mem_105),
    .io_async_mem_106(source_io_async_mem_106),
    .io_async_mem_107(source_io_async_mem_107),
    .io_async_mem_108(source_io_async_mem_108),
    .io_async_mem_109(source_io_async_mem_109),
    .io_async_mem_110(source_io_async_mem_110),
    .io_async_mem_111(source_io_async_mem_111),
    .io_async_mem_112(source_io_async_mem_112),
    .io_async_mem_113(source_io_async_mem_113),
    .io_async_mem_114(source_io_async_mem_114),
    .io_async_mem_115(source_io_async_mem_115),
    .io_async_mem_116(source_io_async_mem_116),
    .io_async_mem_117(source_io_async_mem_117),
    .io_async_mem_118(source_io_async_mem_118),
    .io_async_mem_119(source_io_async_mem_119),
    .io_async_mem_120(source_io_async_mem_120),
    .io_async_mem_121(source_io_async_mem_121),
    .io_async_mem_122(source_io_async_mem_122),
    .io_async_mem_123(source_io_async_mem_123),
    .io_async_mem_124(source_io_async_mem_124),
    .io_async_mem_125(source_io_async_mem_125),
    .io_async_mem_126(source_io_async_mem_126),
    .io_async_mem_127(source_io_async_mem_127),
    .io_async_ridx(source_io_async_ridx),
    .io_async_widx(source_io_async_widx),
    .io_async_safe_ridx_valid(source_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(source_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(source_io_async_safe_source_reset_n),
    .io_async_safe_sink_reset_n(source_io_async_safe_sink_reset_n)
  );
  AsyncQueueSink sink ( // @[AsyncQueue.scala 225:22]
    .clock(sink_clock),
    .reset(sink_reset),
    .io_deq_ready(sink_io_deq_ready),
    .io_deq_valid(sink_io_deq_valid),
    .io_deq_bits(sink_io_deq_bits),
    .io_async_mem_0(sink_io_async_mem_0),
    .io_async_mem_1(sink_io_async_mem_1),
    .io_async_mem_2(sink_io_async_mem_2),
    .io_async_mem_3(sink_io_async_mem_3),
    .io_async_mem_4(sink_io_async_mem_4),
    .io_async_mem_5(sink_io_async_mem_5),
    .io_async_mem_6(sink_io_async_mem_6),
    .io_async_mem_7(sink_io_async_mem_7),
    .io_async_mem_8(sink_io_async_mem_8),
    .io_async_mem_9(sink_io_async_mem_9),
    .io_async_mem_10(sink_io_async_mem_10),
    .io_async_mem_11(sink_io_async_mem_11),
    .io_async_mem_12(sink_io_async_mem_12),
    .io_async_mem_13(sink_io_async_mem_13),
    .io_async_mem_14(sink_io_async_mem_14),
    .io_async_mem_15(sink_io_async_mem_15),
    .io_async_mem_16(sink_io_async_mem_16),
    .io_async_mem_17(sink_io_async_mem_17),
    .io_async_mem_18(sink_io_async_mem_18),
    .io_async_mem_19(sink_io_async_mem_19),
    .io_async_mem_20(sink_io_async_mem_20),
    .io_async_mem_21(sink_io_async_mem_21),
    .io_async_mem_22(sink_io_async_mem_22),
    .io_async_mem_23(sink_io_async_mem_23),
    .io_async_mem_24(sink_io_async_mem_24),
    .io_async_mem_25(sink_io_async_mem_25),
    .io_async_mem_26(sink_io_async_mem_26),
    .io_async_mem_27(sink_io_async_mem_27),
    .io_async_mem_28(sink_io_async_mem_28),
    .io_async_mem_29(sink_io_async_mem_29),
    .io_async_mem_30(sink_io_async_mem_30),
    .io_async_mem_31(sink_io_async_mem_31),
    .io_async_mem_32(sink_io_async_mem_32),
    .io_async_mem_33(sink_io_async_mem_33),
    .io_async_mem_34(sink_io_async_mem_34),
    .io_async_mem_35(sink_io_async_mem_35),
    .io_async_mem_36(sink_io_async_mem_36),
    .io_async_mem_37(sink_io_async_mem_37),
    .io_async_mem_38(sink_io_async_mem_38),
    .io_async_mem_39(sink_io_async_mem_39),
    .io_async_mem_40(sink_io_async_mem_40),
    .io_async_mem_41(sink_io_async_mem_41),
    .io_async_mem_42(sink_io_async_mem_42),
    .io_async_mem_43(sink_io_async_mem_43),
    .io_async_mem_44(sink_io_async_mem_44),
    .io_async_mem_45(sink_io_async_mem_45),
    .io_async_mem_46(sink_io_async_mem_46),
    .io_async_mem_47(sink_io_async_mem_47),
    .io_async_mem_48(sink_io_async_mem_48),
    .io_async_mem_49(sink_io_async_mem_49),
    .io_async_mem_50(sink_io_async_mem_50),
    .io_async_mem_51(sink_io_async_mem_51),
    .io_async_mem_52(sink_io_async_mem_52),
    .io_async_mem_53(sink_io_async_mem_53),
    .io_async_mem_54(sink_io_async_mem_54),
    .io_async_mem_55(sink_io_async_mem_55),
    .io_async_mem_56(sink_io_async_mem_56),
    .io_async_mem_57(sink_io_async_mem_57),
    .io_async_mem_58(sink_io_async_mem_58),
    .io_async_mem_59(sink_io_async_mem_59),
    .io_async_mem_60(sink_io_async_mem_60),
    .io_async_mem_61(sink_io_async_mem_61),
    .io_async_mem_62(sink_io_async_mem_62),
    .io_async_mem_63(sink_io_async_mem_63),
    .io_async_mem_64(sink_io_async_mem_64),
    .io_async_mem_65(sink_io_async_mem_65),
    .io_async_mem_66(sink_io_async_mem_66),
    .io_async_mem_67(sink_io_async_mem_67),
    .io_async_mem_68(sink_io_async_mem_68),
    .io_async_mem_69(sink_io_async_mem_69),
    .io_async_mem_70(sink_io_async_mem_70),
    .io_async_mem_71(sink_io_async_mem_71),
    .io_async_mem_72(sink_io_async_mem_72),
    .io_async_mem_73(sink_io_async_mem_73),
    .io_async_mem_74(sink_io_async_mem_74),
    .io_async_mem_75(sink_io_async_mem_75),
    .io_async_mem_76(sink_io_async_mem_76),
    .io_async_mem_77(sink_io_async_mem_77),
    .io_async_mem_78(sink_io_async_mem_78),
    .io_async_mem_79(sink_io_async_mem_79),
    .io_async_mem_80(sink_io_async_mem_80),
    .io_async_mem_81(sink_io_async_mem_81),
    .io_async_mem_82(sink_io_async_mem_82),
    .io_async_mem_83(sink_io_async_mem_83),
    .io_async_mem_84(sink_io_async_mem_84),
    .io_async_mem_85(sink_io_async_mem_85),
    .io_async_mem_86(sink_io_async_mem_86),
    .io_async_mem_87(sink_io_async_mem_87),
    .io_async_mem_88(sink_io_async_mem_88),
    .io_async_mem_89(sink_io_async_mem_89),
    .io_async_mem_90(sink_io_async_mem_90),
    .io_async_mem_91(sink_io_async_mem_91),
    .io_async_mem_92(sink_io_async_mem_92),
    .io_async_mem_93(sink_io_async_mem_93),
    .io_async_mem_94(sink_io_async_mem_94),
    .io_async_mem_95(sink_io_async_mem_95),
    .io_async_mem_96(sink_io_async_mem_96),
    .io_async_mem_97(sink_io_async_mem_97),
    .io_async_mem_98(sink_io_async_mem_98),
    .io_async_mem_99(sink_io_async_mem_99),
    .io_async_mem_100(sink_io_async_mem_100),
    .io_async_mem_101(sink_io_async_mem_101),
    .io_async_mem_102(sink_io_async_mem_102),
    .io_async_mem_103(sink_io_async_mem_103),
    .io_async_mem_104(sink_io_async_mem_104),
    .io_async_mem_105(sink_io_async_mem_105),
    .io_async_mem_106(sink_io_async_mem_106),
    .io_async_mem_107(sink_io_async_mem_107),
    .io_async_mem_108(sink_io_async_mem_108),
    .io_async_mem_109(sink_io_async_mem_109),
    .io_async_mem_110(sink_io_async_mem_110),
    .io_async_mem_111(sink_io_async_mem_111),
    .io_async_mem_112(sink_io_async_mem_112),
    .io_async_mem_113(sink_io_async_mem_113),
    .io_async_mem_114(sink_io_async_mem_114),
    .io_async_mem_115(sink_io_async_mem_115),
    .io_async_mem_116(sink_io_async_mem_116),
    .io_async_mem_117(sink_io_async_mem_117),
    .io_async_mem_118(sink_io_async_mem_118),
    .io_async_mem_119(sink_io_async_mem_119),
    .io_async_mem_120(sink_io_async_mem_120),
    .io_async_mem_121(sink_io_async_mem_121),
    .io_async_mem_122(sink_io_async_mem_122),
    .io_async_mem_123(sink_io_async_mem_123),
    .io_async_mem_124(sink_io_async_mem_124),
    .io_async_mem_125(sink_io_async_mem_125),
    .io_async_mem_126(sink_io_async_mem_126),
    .io_async_mem_127(sink_io_async_mem_127),
    .io_async_ridx(sink_io_async_ridx),
    .io_async_widx(sink_io_async_widx),
    .io_async_safe_ridx_valid(sink_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(sink_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(sink_io_async_safe_source_reset_n),
    .io_async_safe_sink_reset_n(sink_io_async_safe_sink_reset_n)
  );
  assign io_enq_ready = source_io_enq_ready; // @[AsyncQueue.scala 232:17]
  assign io_deq_valid = sink_io_deq_valid; // @[AsyncQueue.scala 233:10]
  assign io_deq_bits = sink_io_deq_bits; // @[AsyncQueue.scala 233:10]
  assign source_clock = io_enq_clock; // @[AsyncQueue.scala 227:16]
  assign source_reset = io_enq_reset; // @[AsyncQueue.scala 228:16]
  assign source_io_enq_valid = io_enq_valid; // @[AsyncQueue.scala 232:17]
  assign source_io_enq_bits = io_enq_bits; // @[AsyncQueue.scala 232:17]
  assign source_io_async_ridx = sink_io_async_ridx; // @[AsyncQueue.scala 234:17]
  assign source_io_async_safe_ridx_valid = sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 234:17]
  assign source_io_async_safe_sink_reset_n = sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 234:17]
  assign sink_clock = io_deq_clock; // @[AsyncQueue.scala 229:14]
  assign sink_reset = io_deq_reset; // @[AsyncQueue.scala 230:14]
  assign sink_io_deq_ready = io_deq_ready; // @[AsyncQueue.scala 233:10]
  assign sink_io_async_mem_0 = source_io_async_mem_0; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_1 = source_io_async_mem_1; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_2 = source_io_async_mem_2; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_3 = source_io_async_mem_3; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_4 = source_io_async_mem_4; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_5 = source_io_async_mem_5; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_6 = source_io_async_mem_6; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_7 = source_io_async_mem_7; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_8 = source_io_async_mem_8; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_9 = source_io_async_mem_9; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_10 = source_io_async_mem_10; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_11 = source_io_async_mem_11; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_12 = source_io_async_mem_12; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_13 = source_io_async_mem_13; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_14 = source_io_async_mem_14; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_15 = source_io_async_mem_15; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_16 = source_io_async_mem_16; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_17 = source_io_async_mem_17; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_18 = source_io_async_mem_18; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_19 = source_io_async_mem_19; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_20 = source_io_async_mem_20; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_21 = source_io_async_mem_21; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_22 = source_io_async_mem_22; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_23 = source_io_async_mem_23; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_24 = source_io_async_mem_24; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_25 = source_io_async_mem_25; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_26 = source_io_async_mem_26; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_27 = source_io_async_mem_27; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_28 = source_io_async_mem_28; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_29 = source_io_async_mem_29; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_30 = source_io_async_mem_30; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_31 = source_io_async_mem_31; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_32 = source_io_async_mem_32; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_33 = source_io_async_mem_33; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_34 = source_io_async_mem_34; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_35 = source_io_async_mem_35; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_36 = source_io_async_mem_36; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_37 = source_io_async_mem_37; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_38 = source_io_async_mem_38; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_39 = source_io_async_mem_39; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_40 = source_io_async_mem_40; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_41 = source_io_async_mem_41; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_42 = source_io_async_mem_42; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_43 = source_io_async_mem_43; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_44 = source_io_async_mem_44; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_45 = source_io_async_mem_45; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_46 = source_io_async_mem_46; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_47 = source_io_async_mem_47; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_48 = source_io_async_mem_48; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_49 = source_io_async_mem_49; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_50 = source_io_async_mem_50; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_51 = source_io_async_mem_51; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_52 = source_io_async_mem_52; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_53 = source_io_async_mem_53; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_54 = source_io_async_mem_54; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_55 = source_io_async_mem_55; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_56 = source_io_async_mem_56; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_57 = source_io_async_mem_57; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_58 = source_io_async_mem_58; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_59 = source_io_async_mem_59; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_60 = source_io_async_mem_60; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_61 = source_io_async_mem_61; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_62 = source_io_async_mem_62; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_63 = source_io_async_mem_63; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_64 = source_io_async_mem_64; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_65 = source_io_async_mem_65; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_66 = source_io_async_mem_66; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_67 = source_io_async_mem_67; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_68 = source_io_async_mem_68; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_69 = source_io_async_mem_69; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_70 = source_io_async_mem_70; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_71 = source_io_async_mem_71; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_72 = source_io_async_mem_72; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_73 = source_io_async_mem_73; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_74 = source_io_async_mem_74; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_75 = source_io_async_mem_75; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_76 = source_io_async_mem_76; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_77 = source_io_async_mem_77; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_78 = source_io_async_mem_78; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_79 = source_io_async_mem_79; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_80 = source_io_async_mem_80; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_81 = source_io_async_mem_81; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_82 = source_io_async_mem_82; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_83 = source_io_async_mem_83; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_84 = source_io_async_mem_84; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_85 = source_io_async_mem_85; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_86 = source_io_async_mem_86; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_87 = source_io_async_mem_87; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_88 = source_io_async_mem_88; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_89 = source_io_async_mem_89; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_90 = source_io_async_mem_90; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_91 = source_io_async_mem_91; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_92 = source_io_async_mem_92; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_93 = source_io_async_mem_93; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_94 = source_io_async_mem_94; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_95 = source_io_async_mem_95; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_96 = source_io_async_mem_96; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_97 = source_io_async_mem_97; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_98 = source_io_async_mem_98; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_99 = source_io_async_mem_99; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_100 = source_io_async_mem_100; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_101 = source_io_async_mem_101; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_102 = source_io_async_mem_102; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_103 = source_io_async_mem_103; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_104 = source_io_async_mem_104; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_105 = source_io_async_mem_105; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_106 = source_io_async_mem_106; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_107 = source_io_async_mem_107; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_108 = source_io_async_mem_108; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_109 = source_io_async_mem_109; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_110 = source_io_async_mem_110; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_111 = source_io_async_mem_111; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_112 = source_io_async_mem_112; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_113 = source_io_async_mem_113; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_114 = source_io_async_mem_114; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_115 = source_io_async_mem_115; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_116 = source_io_async_mem_116; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_117 = source_io_async_mem_117; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_118 = source_io_async_mem_118; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_119 = source_io_async_mem_119; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_120 = source_io_async_mem_120; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_121 = source_io_async_mem_121; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_122 = source_io_async_mem_122; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_123 = source_io_async_mem_123; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_124 = source_io_async_mem_124; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_125 = source_io_async_mem_125; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_126 = source_io_async_mem_126; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_mem_127 = source_io_async_mem_127; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_widx = source_io_async_widx; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_safe_widx_valid = source_io_async_safe_widx_valid; // @[AsyncQueue.scala 234:17]
  assign sink_io_async_safe_source_reset_n = source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 234:17]
endmodule
